Integrated circuits are chemically and physically integrated into a substrate, such as a silicon or gallium arsenide wafer, by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be electrically conductive, or formed to be semi-electrically conductive and of different conductivity types. Such regions are utilized to form electronic components or devices, such as transistors, diodes and capacitors. Thousands of these devices are formed essentially simultaneously on the surface of a single wafer of semiconductor material during processing.
Initially, each of the electronic devices are electrically isolated from others. But later in the fabrication sequence, specific devices are electrically interconnected so as to implement the desired circuit function. Throughout the evolution of integrated circuits, the aim of component device scaling has essentially been two-fold: (1) to increase circuit performance (mainly by increasing circuit speed), and (2) to increase the functional complexity of the circuits. At the outset, scaling down of active device sizes was a very effective means of achieving each of these goals. Eventually, the scaling of active devices became less profitable, as the limitations of the circuit speed and maximum functional density came to depend more on the characteristics of the electrical interconnects of the devices rather than on the scale of the devices themselves. In addition, the aspects of silicon utilization, chip costs, and ease of flexibility of integrated circuit design were also adversely affected by electrical interconnect-technology restrictions. The approaches to lifting these limitations have predominantly involved the implementation of vertical stacking or integration of devices and their associated electrical interconnection, commonly referred to as multilevel-interconnect schemes.
One drawback of multilevel interconnection is a loss of topological planarity. Loss of planarity results in associated problems in photolithography and etch, as well as other problems. To alleviate these problems, the wafer is "planarized" at various points in the process to minimize non-planar topography and its adverse effects. As additional levels are added to multilevel-interconnection schemes and circuit features are scaled to submicron dimensions, the required degree of planarization increases. Such planarization can be implemented in either the conductor or the dielectric layers. This invention is specific to planarizing techniques associated with the dielectric insulating materials.
One method used to provide wafer surface planarity in a dielectric layer includes forming an oxide layer such as borophosphosilicate glass (BPSG) on a wafer surface, then heating the wafer to reflow and planarize the oxide layer. Such a technique is commonly referred to as "reflow", and was an effective means of planarizing with comparatively large device geometries. However, as technology allowed for smaller device feature sizes, reflow methods produced unsatisfactory degrees of planarization.
Another method used to produce a planar wafer surface is to initially spin coat the wafer with photoresist. The spin coating of this material on the wafer surface fills the low points and produces a planar upper surface from which to start. Next, a dry etch which removes photoresist and oxide at a rate sufficiently close to 1:1, removes the photoresist and the high points of the wafer, thereby producing a substantially planarized oxide layer on the wafer surface.
Most recently, chemical-mechanical polishing (CMP) processes have been used to planarize the surface of wafer in preparation for device fabrication. The CMP process involves holding a thin, flat wafer of semiconductor material against a rotating wetted polishing pad surface under controlled downward pressure. A polishing slurry, such as a mixture of either a basic or an acidic solution, is used as a chemical etch component in combination with alumina or silica particles. A rotating polishing head or wafer carrier is typically used to hold the wafer under controlled pressure against a rotating polishing platen. The polishing platen is typically covered with a polishing pad material, such as blown polyurethane. Such polishing employs both chemical and mechanical aspects of removal. In one aspect, the liquid portion of the slurry chemically removes, loosens or modifies the composition of the material on the wafer which is desired to be removed. The particles or grit within the slurry, in combination with the rotating polishing pad, then physically remove the chemically modified material from the wafer.
The effectiveness of chemical-mechanical polishing for planarization is in part dependent upon its ability to remove high areas faster than low areas, something which is commonly referred to as CMP "selectivity". Such is typically defined as the ratio of the high area removal rate to the low area removal rate. It is preferred to have CMP selectivity as high as possible to reduce doming, and allow thinner oxide deposition over the topography.
CMP selectivity is a function of pad compressibility, slurry, process pressure, platen speed, differential height, and the distance of measured low and high points, and pattern density, as is well perceived by people of skill in the CMP art. In conventional planarization processes, including those of CMP, an undesirably thick oxide layer is deposited before chemical-mechanical polishing to enable full planarization of the topography. The minimum pre-CMP oxide thickness is generally determined by: EQU Oxide=XO+X1+S(t)*T (1)
where:
X0=highest underlayer step PA1 X1=remain BPSG thickness over highest step PA1 S(t)=low area removal rate (function of time) PA1 H(t)=high area removal rate (function of time) PA1 T=polishing time in minutes=X0/H(t)+t' PA1 t'=over CMP time to account for film/CMP uniformity.
It can be seen from Equation (1) that it is desirable to have a small low area removal rate, S(t), to minimize the oxide thickness required for full planarization.
The term S(t)*T can be rewritten in terms of selectivity as follows: ##EQU1##
Since the low area removal rate, S(t), is inversely proportional to the selectivity, as selectivity is improved the net removal from the low areas is reduced.
Alternately considered, present CMP technology essentially requires that the net removed thickness over the highestmost projection be greater than 1.5 times the greatest topographical distance in order to achieve adequate planarization. Such is described with reference to FIGS. 1 and 2. There illustrated is a semiconductor wafer fragment indicated generally by reference numeral 10. Wafer fragment 10 is comprised of a bulk substrate 12 and an electrically conductive metal or polysilicon runner 14. A conformal layer 16 of insulating material is provided to a first thickness over substrate 12, which has a non-planar topography the result of runner 14. Such results in the illustrated projecting portion 18 of insulating material 16 above runner 14. Insulating material 16 would typically be SiO.sub.2 which has been doped with boron and/or phosphorus. For purposes of the continuing discussion, conductive runner 14 has an upper surface 20 which comprises a highestmost projection of the non-planar topography of wafer 10. Likewise, bulk substrate surface 12 includes an uppermost surface 22 which, for purposes of the continuing discussion, provides a lowestmost surface or indentation for purposes of characterizing the non-planar wafer topography atop which layer 16 is provided. Such surfaces have a defined maximum distance therebetween designated by letter "A". Letter "B" designates the thickness of deposited BPSG layer 16. Letter "F" depicts the greatest topological distance of layer 16 (i.e., the difference between the highest and lowestmost points of layer 16) immediately prior to the CMP step depicted by FIG. 2.
In many instances do to increasing circuit density, "F" will be greater than "A". This results from less than complete 100% conformal step coverage in the deposition of layer 16. For example as the distance between adjoining runners 14 diminishes, less material will be deposited in the low points (surfaces 22) than is deposited on the high points (surfaces 20). Subsequent steps, such as reflow or other heat treatments, leave a distance "F" which can and will typically be greater than distance "A".
FIG. 2 illustrates the FIG. 1 wafer after chemical-mechanical polishing. Distance "E" depicts the post CMP thickness of layer 16 above the highest elevation surface 20, Distance "E" is a parameter which the process designer selects based upon criteria not particularly germane to this disclosure. Thickness "B" is selected to arrive at the desired distance "E". Such selection is dependent upon the present capabilities of chemical-mechanical polishing processes. Presently, thickness "B" is selected such than B-E is greater than 1.5 times F, where F is the greatest topographical distance immediately prior to the CMP step.
Such effectively results in an increase in the vertical volume of processing material on the wafer. If possible, it would be desirable to reduce the vertical quantity of interlevel dielectric material 16 while still achieving the high degree of planarity provided by chemical-mechanical polishing processes.
In order to reduce the amount of material polished, it is necessary to reduce the undesirable removal of material in the global low levels of the wafer that occurs at the same time that global high levels of the wafer are being polished. Such occurs in part because the polishing pad is not perfectly flat or rigid, but rather conforms by bending to contact low areas of the wafer as well as high areas of the wafer upon polishing. Chemical mechanical polishing pressure is of course greatest at or against the highest points. But nevertheless, polishing pressure does result in some chemical-mechanical polishing action of the global low areas of the wafer at the same time that the high areas of the wafer are being removed. It would be desirable to minimize removal of material from these lower global wafer areas, for example the scribe areas between to dies.
FIG. 3 is a three-dimensional graphical representation of a prior art chemical-mechanical polishing process. Such involved a semiconductor wafer having an average distance between highestmost projections and lowestmost indentations of 0.8 microns, thus defining a highly nonplanar topography. A layer of BPSG deposited to a thickness of 2.6 microns was provided atop the wafer, and was chemical-mechanical polished by prior art techniques to achieve global planarization. The polishing slurry comprised colloidal silica slurry, and the pad comprised a polyethylene polymer. FIG. 3 represents essentially seven snapshots in time of the degree of planarization of that BPSG layer during the chemical-mechanical polishing process towards the goal of achieving substantial wafer planarity. The illustrated mountain-looking projection at the far left represents a feature on the wafer at the start of chemical-mechanical polishing, while the relatively flatter surface at the far right of the graph represents the finished chemical-mechanical polished product. The Z axis is fixed with respect to the wafer surface. The zero plane of the Z axis represents the starting point of the globally low areas of the oxide surface prior to chemical-mechanical polishing. It would be ideal if planarization of the illustrated mountains could be achieved downwardly to the point of being flush with the illustrated zero Z plane, meaning none of the global low area is removed while the high areas are effectively flattened to the zero Z plane. Yet as indicated by the far right (seventh) data point on the graph, considerable removal below the zero Z plane has occurred to achieve desired planarization. Further, removal below the zero Z plane begins almost immediately in the prior art process, as represented by the second discrete mountain-like projection extending to or starting from beneath the zero Z plane.
It would be desirable to improve upon such techniques and provide chemical-mechanical polishing processing steps for planarizing interlevel dielectrics which minimize the required removal rate of material in the global low, scribe area below the illustrated Z axis zero plane.